The present invention relates to a data processing unit with pipeline control, and more particularly to a data processing unit which executes variable length instructions having operand specifiers for specifying addressing modes of operands issued independently from operation codes for ascertaining operations.
In a variable length instruction architecture, the instruction length varies even if the length of the operation code is fixed. The leading field of the instruction is an operation code but the other fields have various meanings. Accordingly, the meanings of the fields in the instruction are not uniquely defined. Furthermore, since the operand specifiers in the instruction have variable lengths depending on the addressing mode, the instruction length is variable even if the operation code is fixed.
In an instruction decoding unit which handles such variable length instruction architecture, if an instruction is fetched and decoded parallelly, a large scale hardware is required and a complex control is necessary.
In a system in which an instruction is fetched and decoded one or a plurality of predetermined lengths of units at a time, a long time is required to decode the instruction and hence high speed processing can not be attained. For example, if a basic unit comprises eight bits (byte), a basic instruction has a three to seven-byte length. If the instruction is decoded in synchronism with a machine cycle, the machine cycles which are equal in number to the number of bytes of the instruction are necessary to decode the instruction.
Thus, in the data processing unit which handles the variable length instruction architecture, it is an important factor to increase the speed of the processing of the instruction decoding operation to attain an efficient pipeline processing.